1. Field of the Invention
The present invention relates to an output buffer circuit and more specifically to an output buffer circuit for a memory. More specifically, this invention relates to an output buffer circuit for a memory wherein one of a pair of complementarily-connected MOS transistors is divided into two smaller-sized MOS transistors so that the load capacitance is discharged during switching through two paths through the divided MOS transistors, one of which is delayed relative to the other.
2. Description of the Prior Art
Conventionally, an MOS memory is widely used as a storage device of an electronic computer. An MOS memory has a great number of memory cells made up of MOS transistors which are arranged to form a memory matrix. Information is written into or read from the memory matrix in accordance with any selected addresses. To read any given information from the above-mentioned memory cells, predetermined addresses are selected by a selector and the data are read through an output buffer circuit under control of a read/write control circuit. The output buffer circuit outputs data signals in accordance with a control signal such as an output disable signal applied to the output buffer circuit through a logic circuit.
In the above-mentioned output buffer circuit, the data signal and the output disable signal are applied to each of the gates of a pair of complementarily-connected P-channel and N-channel MOS transistors through the logic circuit and the data signal is outputted from an intermediate junction point between the two drains of the MOS transistors. The source of one of the two MOS transistors is connected to a power supply and the source of the other of the two MOS transistors is connected to ground through a lead inductance caused by the aluminum wires and/or the bonding wires within a semiconductor chip and/or the lead wires of a lead frame. A load capacitance having a capacity determined in accordance with the MOS memory standard is connected to the output terminal thereof. When the load capacitance is charged or discharged through the lead inductance during the switching operaton of the buffer circuit, an induced voltage is inevitably generated across the lead inductance. This induced voltage changes the potential of the reference voltage of the other circuits connected to the memory matrix. In particular, when several output buffer circuits are incorporated within the memory unit, plural induced voltages are generated simultaneously to a high voltage such as several hundreds millivolts or more.
On the other hand, since the input levels of the control signals supplied to the other circuits are determined by the TTL level, the control signals are distorted or disturbed by the induced voltage. In this connection, it is possible to reduce the induced voltage by decreasing the size of the MOS transistor. However, this results in a serious problem such that the access time to the memory is lengthened.
The circuit configuration of the prior art output buffer circuit will be described in further detail hereinafter with reference to the attached drawings in the detailed description of the preferred embodiments.